1. Field of the Invention
The present invention relates to techniques for improving computer system performance. More specifically, the present invention relates to a method and an apparatus for improving the effectiveness of prefetching during scout mode by selectively waiting for specific load misses to return from L2 cache during scout mode.
2. Related Art
Advances in semiconductor fabrication technology have given rise to dramatic increases in microprocessor clock speeds. This increase in microprocessor clock speeds has not been matched by a corresponding increase in memory access speeds. Hence, the disparity between microprocessor clock speeds and memory access speeds continues to grow, and is beginning to create significant performance problems. Execution profiles for fast microprocessor systems show that a large fraction of execution time is spent not within the microprocessor core, but within memory structures outside of the microprocessor core. This means that the microprocessor systems spend a large fraction of time waiting for memory references to complete instead of performing computational operations.
When a memory reference, such as a load operation, generates a cache miss, the subsequent access to level-two (L2) cache or to main memory can require dozens or hundreds of clock cycles to complete, during which time the processor is typically idle, performing no useful work.
A number of techniques are presently used (or have been proposed) to hide this cache-miss latency. Some processors support out-of-order execution, in which instructions are kept in an issue queue, and are issued “out-of-order” when operands become available. Unfortunately, existing out-of-order designs have a hardware complexity that grows quadratically with the size of the issue queue. Practically speaking, this constraint limits the number of entries in the issue queue to one or two hundred, which is not sufficient to hide memory latencies as processors continue to get faster. Moreover, constraints on the number of physical registers that can be used for register renaming purposes during out-of-order execution also limit the effective size of the issue queue.
Some processor designers have proposed entering a “scout mode” to hide the cache-miss latency. If the processor encounters a stall condition, such as a cache miss, instead of waiting for the cache miss to be resolved, the processor generates a checkpoint and enters scout mode. In scout mode, instructions are speculatively executed to prefetch future memory operations, but results are not committed to the architectural state of the processor. When the stall condition is finally resolved, the system uses the checkpoint to resume execution in normal-execution mode from the instruction that originally encountered the stall condition. By allowing the processor to continue to perform prefetches during stall conditions, scout mode can significantly increase the amount of work the processor completes.
Unfortunately, proposed systems that use scout mode do not always achieve optimal performance. In particular, during scout mode it is not always beneficial to continue executing instructions when a load misses in the L1 cache. In some cases, it may be better to wait for the corresponding load value to return from the L2 cache before resuming execution in scout mode because the load value may be used in computing addresses to be prefetched. If the system does not wait for such load values to return, the system will not prefetch these addresses, which can lead to suboptimal performance.
Hence, what is needed is a method and an apparatus for executing instructions in scout mode without the above-described performance problem.